1. Field of the Invention
This invention pertains generally to dynamic semiconductor memory, and more particularly to dynamic memory having self-refresh circuitry.
2. Description of Related Art
Dynamic random access memory (DRAM) stores each bit of data in a separate capacitor within the integrated circuit. In response to the leakage of the capacitors, the information stored in response to capacitor charge must be periodically refreshed. In view of the non-static nature of these memories they are referred to as dynamic memories. The refresh operations of the memory can be performed in response to signals from external circuits, and/or in response to internal refresh circuits.
FIG. 1 depicts a block diagram for a typical dynamic memory array, showing four arrays of memory cells between each of which are Bit Line Sense Amplifiers (BLSA) and equalizers (EQ), such as Bit Line Equalizers. At the bottom of the schematic are shown circuitry for generating Sense Amplifier Activation signals (SAPN controlling both P and N channel sense amplifier (SAP) and (SAN), or equivalent), isolator control signals (ISO), and Bit Line Equalization (BLEQ) signals.
FIG. 2 is a detailed circuit diagram of typical BLSA, CSL and EQ circuits. Signals are shown connected in the figure, including bit lines and bit line complement for left and right (BL_L, BLB_L, BL_R, BLB_R), Bit Line Voltage (VBL), Bit Line Equalization (BLEQ), isolation control signal left and right (ISOL and ISOR), input/output and complement (IO, IOB), column select line (CSL), P and N channel sense amplifier enable signals (SAP and SAN signals which are collectively referred to as SAPN), as well as amplifier latch and complement (LA, LAB). A typical memory array comprises multiple cell array blocks, Bit Line Sense Amplifiers (BLSA), Column Select Lines (CSL), Bit Line Equalizers (BLEQ), Isolators, isolator control signal (ISO) and associated control signal generators. During a normal memory operation, the control circuits respond to address and command signals fed from an external source.
FIG. 3 is an example block diagram of a conventional isolation control (ISO) generation scheme. Block selection is seen performed in response to decoding of address and commands from the received address and command buffer. The command buffer controls row address selection (RAS Active), self refresh control (Self-Refresh), including a refresh counter (Refresh Counter), with these signals being received by an address decoder (Address Decoder) whose output controls block selection. The output of the block selection circuit selectively activates: (1) cell array block isolator (ISO Gen.) to prevent interference and unintended disturbance; (2) BLSA and BLEQ (BLEQ Gen.) for the activated cell array block to equalize and amplify information stored in the selected cell array block and eliminate voltage differences on bit lines, while BLSA senses and amplifies the electrical signal differences on bit lines; and (3) controls sense amplifier activation signals SAN, SAP (SAPN Gen.).
FIGS. 4A and 4B are timing diagrams for conventional ISOi generation shown operating for normal and auto-refresh modes in FIG. 4A, and in self-refresh operation in FIG. 4B. It should be noted that auto-refresh is categorized with normal operating modes because auto-refresh uses the internal counter of the memory to refresh its rows, wherein multiple row addresses don't need to be put on the address bus to refresh multiple rows. Accordingly, references to normal operating mode, or modes, includes the operation of auto-refresh in the following discussions.
By way of example, during self-refreshing of a cell array block consisting of 256 word lines, a conventional self-refresh control scheme generates an isolation signal (ISO) 256 times, once for each activated word line of the cell array block, wherein each isolation signal generated swings the control voltage between control signal low and high. It should be appreciated that the current consumed by conventional isolation signals during self-refresh operation is directly proportional to the number of isolation signals generated for self-refresh operation of the 256 word lines. Therefore, current is consumed for each ISO (ISOi-ISOk) transition for a block containing 256 word lines wherein the ISO lines are activated 256 times which comprises 512 transitions (each activation having a first and second transition-edge).
FIG. 5 is an illustrative circuit diagram of a conventional word line driver, shown with multiple blocks on successive tiled sections. It will be appreciated that typical word line drivers comprise plural pre-decoded row address drivers (PXID) and plural word enable (WE) lines. Historically, word enable lines were used to directly control access to memory cells. As the density and complexity of integrated circuit grew, the number of WE lines had grown to a point where the number of WE lines would not physically fit in the integrated circuit and necessitated multi-dimensional access control scheme. In this two dimensional control scheme, each WE line contains information for 8 sub-word lines while PXID further down-selects one sub-word line from 8 sub-word lines. The signal PXID is a driver output for the signal PXI. The signal WEi represents a word enable (WE) signal for a given block or page of memory within the memory device.
It should be appreciated that the ISO generator block is controlled by the output of “Block Selection” which also controls BLEQ generation and SAPN generation for bit line sense amplifiers. The conventional control arrangement thus controls ISO generation with the same block selection as controls the BLEQ and SAPN. Consequently, in the conventional configuration ISO is controlled the same way regardless of whether the array is performing a normal operation or a self-refresh operation.
FIG. 6 illustrates a conventional PXI generation scheme in which one refresh counter controls both normal operation and self-refresh operation through the address decoder (Address Decoder). This control scheme lacks the flexibility to control timing and sequence of PXI or WEI in response to normal operation or self-refresh modes. It will be seen in the figure that the address decoder receives input from the address buffer as well as from the command buffer whose signals are directed to RAS active, self-refresh, and the refresh counter feeding the address decoder. Output from the address decoder drives the PXI, PXID and WEI generation circuits.
FIGS. 7A and 7B are timing diagrams for conventional PXID and WEI generation shown operating for normal and auto-refresh modes in FIG. 7A, and in self-refresh operation in FIG. 7B.
Similar to the situation with ISO generation, the conventional self-refresh control scheme generates pre-decoded row address (PXI or PXID) and main word enable (WE or WEI) signals 256 times each, wherein each PXID and WE signal generated swings the control voltage between control signal low and high. Current consumed by conventional PXID and WE signals during self-refresh operation is directly proportional to the number of PXID and WE signals generated for self-refresh operation of 256 word lines. Conventional PXID and WE generation is shown in FIG. 7A-7B. Therefore, it is seen that current is consumed for each PXID and WE transition, wherein for a block containing 256 word lines each PXID and WE is activated 256 times per block.
Therefore, it is desirable to reduce current consumption within dynamic memory circuits without impacting operating characteristics. The present invention satisfies those needs, as well as others, and overcomes the deficiencies of previously developed power reduction schemes.